1. Field of the Invention
The present invention relates to a sample and hold circuit, and more particularly to the sample and hold circuit which is suitably arranged for a source driver for a liquid crystal panel.
2. Description of the Related Art
The inventors of the present application know a sample and hold circuit for a source driver of a liquid crystal panel which has been heretofore proposed. An example of the known circuit together with its connected liquid crystal panel will be shown in FIG. 1. As shown, numerals 51 and 52 denote sample and hold circuits which are used for feeding an image signal to a liquid crystal panel 53. The sample and hold circuit 51 provides two bidirectional shift registers 511 and 512, a sample and hold unit 513, and an output unit 514. Likewise, the sample and hold circuit 52 provides two bidirectional shift registers 512 and 522, a sample and hold unit 523, and an output unit 524.
The bidirectional shift registers 511, 512, 521, 522 receive serial signals but supply parallel signals. These shift registers respectively take sampling pulses SP1, SP2, SP1' and SP2', shift these sampling pulses in the direction specified in synchronous to the shift clocks .phi.1, .phi.2, .phi.1', .phi.2', and supply these results at respective stages. The apostrophe character "'" designates the inverse or complement of a particular signal having high level (high) and low level (low) states.
Each of the sample and hold units 513 and 523 is composed of a plurality of sample and hold elements. The plurality of sample and hold elements for each sample and hold unit are divided into a first group and a second group. The first group of sample and hold elements receive an analog signal VA as a signal to be sampled and held and the second group of sample and hold elements receive an analog signal VB as a signal to be sampled and held. At each element belonging to the first group of the sample and hold unit 513, an output pulse is applied from each stage of the shift register 511. At each element belonging to the second group of the sample and hold unit 513, an output pulse is applied from each stage of the shift register 512. At each element belonging to the first group of the sample and hold unit 523, an output pulse is applied from each stage of the shift register 521. At each element belonging to the second group of the sample and hold unit 523, an output pulse is applied from each stage of the shift register 521. When such a pulse is applied from the shift register to each sample and hold element, the sample and hold element holds analog signals VA and VB. As shown, the elements of the first group and the elements of the second group are arranged in an alternate manner. In the arrangement, a pair of adjacent sample and hold elements belonging to the first and the second groups receive outputs from the same stages of the two shift registers.
Each of the output units 514 and 524 is composed of a plurality of output circuits, each of which is arranged to have an operational amplifier. The signals VA and VB held in each sample and hold element are supplied to the liquid crystal panel 53 through each output circuit of the output units 514 and 524. Each output circuit of the output unit 514 receives the output signals VA and VB of two sample and hold elements to which output pulses are applied from the same stages of the shift register 511 and 512. Likewise, each output circuit of the output unit 524 receives the output signals VA and VB of a pair of two sample and hold elements into which output pulses are applied from the same stages of the shift registers 521 and 522. Each output circuit serves to select any one of these two signals in response to the control signal CNT and output it.
The liquid crystal panel 53 is composed of a plurality of pixel lines, each of which is arranged to have a plurality of pixels 531 ranged in a horizontal manner. At the pixel lines in odd numbered order counted from the above, an analog signal VA is applied. At the pixel lines in even numbered order counted from the above, an analog signal VB is applied. The analog signals VA and VB are switched to each other in response to the control signal CNT. Which of the lines are to be driven by the analog signals VA and VB are determined by a gate driver 54. The odd-number pixels counted from the left margin of each line are driven by the analog signals VA and VB from the sample and hold circuit 51. The even-number pixels counted from the left margin of each line are driven by the analog signals VA and VB from the sample and hold circuit 52. As shown in FIG. 1, the even-number lines are shifted to the left hand by a half pixel with respect to the odd-number lines located thereabove.
FIG. 2 is a chart showing how the shift clocks .phi.1, .phi.2, .phi.1', and .phi.2' fed to the sample and hold circuits 51 and 52 are operated. Now, it is assumed that these shift registers are both operated at a right-shift mode and the shift register 511 reads a sampling pulse SP1 at the rising timing T2 of the clock .phi.1. On the timing, the sampling pulse is output at the left-end output terminal of the shift register 511. In response to the sampling pulse, the leftmost sample and hold element in the first group of the sample and hold unit 513 receives the analog signal VA and holds it. The signal is fed to the leftmost pixel of the first line through the output unit 514. At a timing T4 located a half clock later than the timing T2, the clock .phi.1' rises. In response, the sampling pulse SP1' is received by the shift register 521. On the timing, the sampling pulse is output at the leftmost output terminal of the first group of the shift register 521. As a result, the leftmost sample and hold element of the sample and hold unit 523 receives and holds the analog signal VA. The signal is fed to the second leftmost pixel of the first line through the output unit 524.
Likewise, on the timing T1, the clock .phi.2 has risen. At a time, the sampling pulse SP2 is taken into the shift register 512. On the timing, the sampling pulse is output from the leftmost output terminal of the shift register 512. In response, the second leftmost sample and hold element of the second group of the sample and hold unit 513 serves to receive and hold the analog signal VB. The analog signal VB is supplied to the leftmost pixel of the second line through the output unit 514. On the timing T3, the clock .phi.2' has risen. At a time, the sampling pulse SP2' is received by the shift register 522. On this timing, the leftmost output terminal of the shift register 522 serves to output a sampling pulse. In response, the second leftmost sample and hold element of the second group of the sample and hold unit 523 serves to receive the analog signal VB and hold it. The signal is supplied to the second leftmost pixel of the second line through the output unit 524. Likewise, each time each shift clock rises, the sampling pulse is shifted within the shift register in a manner to sequentially sample and hold the analog signals VA and VB, which are supplied to each pixel.
The display device arranged to use the liquid crystal panel often needs to reverse the left and the right parts of the display. The reverse display can be realized by executing a sample and hold operation of the analog signals VA and VB in sequence from the rightmost sample and hold element of the sample and hold unit, not from the leftmost sample and hold element. For that purpose, it is just necessary to reverse the shifting direction of the sampling pulse in the shift register into an opposite direction and the phase relation of the shift clocks .phi.1, .phi.1' and .phi.2, .phi.2' as shown in FIG. 3. In other words, the phases of the shift clocks .phi.1 and .phi.2 are just required to be lagged by a half period from the phases of the shift clocks .phi.1' and .phi.2'.
However, the sample and hold circuit known by the inventors of the present applicant has required an external circuit for changing the phases of such shift clocks. The provision of the external circuit results in making the overall device complicated.